1. Field of the Invention
2. Description of Related Art
Advanced interconnections schemes for VLSI (Very Large Scale Integration) multilayer circuits have evolved to the use of copper as the wiring levels and polyimide as the insulators, thus giving the lowest possible conductivity and permitivity, i.e., low resistance and low capacitance. As this copper/polyimide technology has evolved, damascene has become the wiring method of choice. Damascene construction refers to the depositing and planarizing of an insulator, etching an insulator groove or trench to form the wiring structure, plating copper over the insulator structure to fill the groove, and then chemical-mechanical polishing the copper such that it is coplanar with the polyimide, creating the final copper in the polyimide structure. Damascene construction is described in U.S. Pat. No. 4,789,648, assigned to the assignee of the present invention, and which is hereby incorporated by reference. However, it has been found that a nitride layer such as silicon nitride is required over the copper/polyimide structure for multi-level structures in order to deposit the next polyimide layer. In essence, the thin nitride layer acts as an etch stop when etching polyimide, and as a passivation over the copper to minimize and/or eliminate copper oxidation.
In older generations of technologies, the formation of stacked vias, for example, a direct M3 to M1 connection, required an impact to ground rules, that is, the stacked vias required independent definition of all the via and wiring levels in between the levels required to be connected, and therefore, because of minimum image size and overlay, and the concern that the subsequent via had to be within the metal landing pad to eliminate an unwanted shorting region, the density is degraded when a stacked via is applied. Also, the stacked via required multiple wiring connection interfaces and thus, contact and via resistance were an issue. Finally, in order to get around these overlay issues, the stacked via may have required a separate masking level to insure ground rules were maintained.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method for making a stacked through via without any additional masks.
It is another object of the present invention to provide a method for making a stacked through via without any additional interconnection resistance.
A further object of the invention is to provide a method for making a stacked through via without impact to ground rules.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects apparent to those skilled in the art are achieved in the present invention which provides a method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect comprising the steps of:
a) forming a first interconnect region to which contact is to be made;
b) forming a first insulating layer over the interconnect region;
c) forming an etch-stop layer over the first insulating layer;
d) etching the etch stop layer to form an opening at a position over the first interconnect region;
e) forming a second interconnect region in contact with the first insulating layer and above the first interconnect region;
f) forming a second insulating layer over the first insulation layer and the etch stop layer;
g) forming an opening in the second insulating layer, the opening in the second insulating layer overlapping the opening in the etch stop layer;
h) extending the opening in the second insulating layer through the first insulating layer; and
i) filling the openings in the first and second insulating layers with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.
Preferably, the second insulating layer is formed over the second interconnect region. The first interconnect region may comprises a conductive line formed in the first insulating layer and the second interconnect region may include a conductor formed in the first insulating layer, wherein the second interconnect region contacts a portion of the first interconnect region.
Preferably, the opening in the etch stop layer and the first and second insulating layer comprise a first opening. In such case, the method further includes the steps of forming a second opening in the etch stop layer and the second insulating layer overlapping the second interconnect region and filling the second opening with a conductor to create a connection between the second interconnect region and a region above the second insulating layer. Also, the step of forming a second opening in the etch stop layer preferably does not remove any etch stop layer portion adjacent to the second interconnect region and over the first insulating layer.
In another preferred embodiment, the etch stop layer comprises a first etch stop layer and the method further includes the steps of forming a second etch stop layer over the second insulating layer and forming a third insulating layer over the second etch stop layer, and wherein step (g) includes forming openings in the second etch stop layer and the third insulating layer which overlap the opening in the first etch stop layer and step (i) includes filling the openings in the second etch stop layer and the third insulating layer with the conductor to create a connection between the first interconnect region and a region above the third insulating layer. Also, the opening in the first and second etch stop layers and the first, second and third insulating layers may comprise a first opening and the method further includes the steps of forming a second opening in the etch stop layers and the insulating layers overlapping the second interconnect region and filling the second opening with a conductor to create a connection between the second interconnect region and a region above the third insulating layer.
In another aspect, the present invention provides a multilevel wiring structure produced by the aforementioned methods. Such a multilevel wiring comprises a first interconnect region to which contact is to be made, a first insulating layer over the first interconnect region, and an etch-stop layer over the first insulating layer, the etch stop layer having an opening at a position over the first interconnect region. The wiring structure also includes a second interconnect region in contact with the first insulating layer and above and in contact with the first interconnect region and a second insulating layer over the first insulation layer, the etch stop layer and the second interconnect region. An opening in the second insulating layer overlaps the opening in the etch stop layer and extends through the first insulating layer and is filled with a continuous conductor between the first interconnect region and a region above the second insulating layer.
Preferably, the second insulating layer is over the second interconnect region, the first interconnect region comprises a conductive line in the first insulating layer, the second interconnect region includes a conductor in the first insulating layer, and the second interconnect region contacts a portion of the first interconnect region.
In the multilevel wiring structure, the opening in the etch stop layer and the first and second insulating layer may comprise a first opening and the circuit may further include a second opening in the etch stop layer and the second insulating layer overlapping the second interconnect region. The second opening is filled with a continuous conductor to create a connection between the second interconnect region and a region above the second insulating layer. The etch stop layer is adjacent to the second interconnect region and over the first insulating layer.
The etch stop layer may comprise a first etch stop layer and the wiring structure may further include a second etch stop layer over the second insulating layer, a third insulating layer over the second etch stop layer, and an opening in the second etch stop layer and the third insulating layer which overlaps the opening in the first etch stop layer. The openings in the second etch stop layer and the third insulating layer are filled with a continuous conductor between the first interconnect region and a region above the third insulating layer. This wiring may further include a second opening in the etch stop layers and the insulating layers overlapping the second interconnect region, the second opening being filled with a continuous conductor between the second interconnect region and a region above the third insulating layer.
In a further aspect, the present invention provides a method for connecting at least two levels of interconnect vertically spaced from each other comprising the steps of:
a) forming a first interconnect region comprising first and second conductors to which contact is to be made;
b) forming a first insulating layer over said first interconnect region;
c) forming a first via in said first insulating layer and in contact with said first conductor;
d) forming a second interconnect region over said first insulating layer comprising a third conductor in contact with said first via;
e) forming a second insulating layer over said first insulating layer; and
f) forming in said second insulating layer a second via within the perimeter of and in contact with said third conductor and a third via continuously extending further through said first insulating layer and in contact with said second conductor, said portion of said third via being out of contact with said second interconnect region.
Preferably, the method further includes forming in said second interconnect region a fourth conductor out of contact with said first via and a fourth via within the perimeter of and in contact with said fourth conductor.
In a related aspect, the present invention is directed to the multi-level wiring structure produced by the aforementioned method.